A 1.6-to-3.2/4.8 GHz Dual-Modulus Injection-Locked Frequency Multiplier in 0.18 m Digital CMOS
نویسندگان
چکیده
This paper proposes a variable-modulus injectionlocked frequency multiplier for better harmonic suppression. It is more suitable for fully-integrated implementation using low-Q on-chip inductors in digital CMOS than conventional approaches. A prototype dual-modulus frequency doubler/tripler with 1.6GHz input and 3.2GHz/4.8GHz output is implemented in a 0.18 m standard digital CMOS. At 5% locking range, the doubler mode achieves fundamental suppression of 42dB with 2.2mW power consumption from 1V supply; while the tripler mode achieves 40dB suppression at the fundamental and 32dB at the second harmonic, with 3.7mW power consumption from 1V supply. Good phase noise performance is achieved for both doubler and tripler modes.
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